🛰️ Hybrid Analog–FPGA Computing Architecture for Space Instruments

The Challenge: Traditional satellite systems rely on software-based virtualization and containerization to support multiple mission payloads. While companies like Unibap have implemented Linux-based SpaceCloud OS with container isolation, these approaches introduce significant performance penalties through resource contention, context switching overhead, and hypervisor management costs. Studies show that virtualization can increase CPU load substantially while bloating application footprints dramatically compared to optimized implementations.

The Problem: Software multi-tenancy forces multiple tenants to share the same CPUs, memory, and data buses, creating unpredictable performance characteristics. Even with CPU pinning, software schedulers introduce timing jitter that compromises real-time processing requirements. Most critically, virtualization-capable platforms consume power levels far exceeding what's available to small CubeSats, fundamentally excluding them from multi-tenant computing.

The Aerolite Solution: Our architecture implements silicon-native partitioning—similar to having multiple separate microcontrollers on a single board, each dedicated to specific tasks. This hardware-level approach completely eliminates software virtualization overhead, enabling true multi-tenant computing feasible for CubeSats with minimal power budgets. Each tenant operates in complete isolation with zero resource contention and deterministic real-time performance, making every watt count toward actual mission work rather than OS overhead.

The Need: Small satellites collect vastly more raw data than they can downlink. Onboard AI enables spacecraft to filter, compress, and prioritize data—dramatically reducing downlink volume and cost. Real missions like ESA's Φ-sat-1 have proven this concept, using CNNs to mask cloudy scenes before downlink. However, current AI implementations face a fundamental trade-off between computational capability and power efficiency.

Building on NASA's Foundation: NASA and Johns Hopkins APL previously investigated Field-Programmable Mixed-Signal Arrays (FPMA) for reconfigurable analog circuits in spacecraft. While innovative, the FPMA faced limitations including lack of radiation-hardened processes, analog accuracy drift, bandwidth-power trade-offs, and insufficient computational scalability for modern AI workloads.

The Aerolite Innovation: We've evolved NASA's FPMA concept into a computational FPAA architecture optimized for AI acceleration. Our systolic array-inspired analog computing fabric features configurable analog multiply-accumulate (MAC) cells performing localized matrix operations in parallel. This approach leverages modern CMOS-compatible analog fabrics with integrated radiation-hardening, adaptive calibration to mitigate mismatch and drift, and energy-efficient mixed-signal pipelines. The result is dramatic power reduction compared to traditional digital approaches while maintaining computational precision sufficient for satellite AI applications.

The Challenge: Satellites deployed for extended missions—often lasting decades— face the risk of cryptographic obsolescence. During multi-year missions, cryptographic standards can become compromised or outdated. Traditional fixed-hardware systems cannot adapt to these evolving security threats, creating critical vulnerabilities for long-duration space assets.

The Innovation: Our architecture employs FPGAs and FPAAs as the computing core, providing inherent hardware reconfigurability. This capability enables complete gateware updates from the ground, allowing changes to hardware functionality, implementation of new cryptographic algorithms, or responses to emerging security threats—all after launch.

AI-Optimized Transpilation: The system features an AI-optimized Python-to-VHDL transpiler with machine learning-based architecture selection. A Random Forest classifier analyzes cryptographic algorithms and intelligently decides whether to generate parallel (faster, more resources) or sequential (slower, area-efficient) hardware architectures. This creates a "fast lane" from software implementation to hardware deployment, dramatically accelerating crypto-agility.

Beyond Crypto-Agility: Reconfigurability also enables on-orbit repurposing and dynamic fault recovery. If a component fails, the system can reroute signal paths, bypass defective components, and utilize redundant resources to continue operations in degraded mode. Even if a critical instrument fails, the satellite can be entirely reconfigured and repurposed for a different mission utilizing remaining functional subsystems.

The Concept: Digital twin technology creates a virtual counterpart to physical subsystems, enabling diagnostic insight and proactivity unattainable with conventional methods. Our system embeds digital twins of satellite subsystems into the FPGA in the form of transfer functions—providing compact mathematical descriptions of input-to-output relationships with minimum computational overhead.

Two-Stage Recovery Process: The system implements an innovative approach that maximizes uptime while ensuring efficient hardware resource use:

AI Architecture: The fault detection system uses a two-tiered 1D Convolutional Neural Network (CNN) that first detects the presence of a fault, then classifies its type. Through rigorous temporal validation methodology, the system achieves high binary fault detection accuracy with perfect precision and exceptional multi-class classification accuracy.

The Result: This approach enables autonomous fault detection and repair with minimal mission downtime, dramatically extending satellite operational life compared to traditional systems. The satellite becomes a self-healing platform capable of decades-long autonomous operation in the harsh space environment.